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INTEGRATED CIRCUITS
74LV139 Dual 2-to-4 line decoder/demultiplexer
Product specification Supersedes data of 1997 Feb 12 IC24 Data Handbook 1998 Apr 28
Philips Semiconductors
Philips Semiconductors
Product specification
Dual 2-to-4 line decoder/demultiplexer
74LV139
FEATURES
* Wide operating voltage: 1.0 to 5.5 V * Optimized for low voltage applications: 1.0 to 3.6 V * Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V * Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, * Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, * Demultiplexing capability * Two independent 2-to-4 decoders * Multifunction capability * Active LOW mutually exclusive outputs * Output capability: standard * ICC category: MSI
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25C; tr = tf 2.5 ns SYMBOL tPHL/tPLH CI CPD PARAMETER Propagation delay nAn to nYn, nE to nYn Input capacitance Power dissipation capacitance per multiplexer Tamb = 25C Tamb = 25C
APPLICATIONS
* Memory decoding or data-routing * Code conversion
DESCRIPTION
The 74LV139 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT139. The 74LV139 is a dual 2-to-4 line decoder/demultiplexer. This device has two independent decoders, each accepting two binary weighted inputs (nA0 and nA1) and providing four mutually exclusive active LOW outputs (nY0 to nY3). Each decoder has an active LOW enable input (nE). When nE is HIGH, every output is forced HIGH. The enable can be used as the data input for a 1-to-4 demultiplexer application.
CONDITIONS CL = 15 pF; VCC = 3.3 V
TYPICAL 11 10 3.5
UNIT ns pF pF
VCC = 3.3 V VI = GND to VCC1
42
NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in W) PD = CPD x VCC2 x fi ) (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL x VCC2 x fo) = sum of the outputs.
ORDERING INFORMATION
PACKAGES 16-Pin Plastic DIL 16-Pin Plastic SO 16-Pin Plastic SSOP Type II 16-Pin Plastic TSSOP Type I TEMPERATURE RANGE -40C to +125C -40C to +125C -40C to +125C -40C to +125C OUTSIDE NORTH AMERICA 74LV139 N 74LV139 D 74LV139 DB 74LV139 PW NORTH AMERICA 74LV139 N 74LV139 D 74LV139 DB 74LV139PW DH PKG. DWG. # SOT38-4 SOT109-1 SOT338-1 SOT403-1
PIN CONFIGURATION
1E 1 1A0 1A1 1Y0 1Y1 1Y2 1Y3 GND 2 3 4 5 6 7 8 16 VCC 15 2E 14 2A0 13 2A1 9 2Y0
PIN DESCRIPTION
PIN NUMBER 1, 15 2, 3 4, 5, 6, 7 8 12, 11, 10, 9 14, 13 16 SYMBOL 1E, 2E 1A0, 1A1 1Y0 to 1Y3 GND 2Y0 to 2Y3 2A0, 2A1 VCC FUNCTION Enable inputs (active LOW) Address inputs Outputs (active LOW) Ground (0 V) Outputs (active LOW) Address inputs Positive supply voltage
10 2Y1 11 2Y2 12 2Y3
SV00530
1998 Apr 28
2
853-1922 19290
Philips Semiconductors
Product specification
Dual 2-to-4 line decoder/demultiplexer
74LV139
LOGIC DIAGRAM
1
FUNCTIONAL DIAGRAM
1Y0 1E 1Y 0 4 5 6 7 12 11 14 10 13 2E 2Y 3 9 2Y3 15 1 1E 2Y0 2A0 2A1 2Y1
DECODER
4 5
2 3
1A0 1A1
DECODER
1Y1 1Y2 1Y3
2 3
1A 0 1A 1
1Y 1 1Y 2 1Y 3 2Y 0
6 7
12
14 13
2A 0 2A 1
2Y 1 2Y 2
11
2Y2
10 9
SV00531
15
2E
SV00534
LOGIC SYMBOL (IEEE/IEC)
DX 2 0 1 0 G -- 3 0 1 4 2 1 2 X/Y 0 1 4
5
5
3
2 3
6 7
3
2 3
6 7
1
1
EN
DX 14 0 0 G -- 3 13 1
0 1
12 14 1 2
X/Y
0 1
12
11
11
2 3 (a)
10 9
13
2 3 (b)
10 9
15
15
EN
SV00532
FUNCTION TABLE
INPUTS nE H L L L L NOTES: H = HIGH voltage level L = LOW voltage level X = don't care nA0 X L H L H nA1 X L L H H nY0 H L H H H nY1 H H L H H OUTPUTS nY2 H H H L H nY3 H H H H L
1998 Apr 28
3
Philips Semiconductors
Product specification
Dual 2-to-4 line decoder/demultiplexer
74LV139
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VI VO Tamb PARAMETER DC supply voltage Input voltage Output voltage Operating ambient temperature range in free air See DC and AC characteristics VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V to 5.5V CONDITIONS See Note 1 MIN 1.0 0 0 -40 -40 - - - - - - - - TYP 3.3 - - MAX 5.5 VCC VCC +85 +125 500 200 100 50 UNIT V V V C
tr, tf
Input rise and fall times
ns/V
NOTE: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V). SYMBOL VCC "IIK "IOK "IO "IGND, "ICC Tstg PARAMETER DC supply voltage DC input diode current DC output diode current DC output source or sink current - standard outputs DC VCC or GND current for types with - standard outputs Storage temperature range Power dissipation per package - plastic DIL - plastic mini-pack (SO) - plastic shrink mini-pack (SSOP and TSSOP) for temperature range: -40 to +125C above +70C derate linearly with 12 mW/K above +70C derate linearly with 8 mW/K above +60C derate linearly with 5.5 mW/K VI < -0.5 or VI > VCC + 0.5V VO < -0.5 or VO > VCC + 0.5V -0.5V < VO < VCC + 0.5V CONDITIONS RATING -0.5 to +7.0 20 50 25 UNIT V mA mA mA
50 -65 to +150 750 500 400
mA C
PTOT
mW
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Apr 28
4
Philips Semiconductors
Product specification
Dual 2-to-4 line decoder/demultiplexer
74LV139
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN VCC = 1.2 V VIH HIGH level Input voltage VCC = 2.0 V VCC = 2.7 to 3.6 V VCC = 4.5 to 5.5 V VCC = 1.2 V VIL LOW level Input voltage VCC = 2.0 V VCC = 2.7 to 3.6 V VCC = 4.5 to 5.5 VCC = 1.2 V; VI = VIH or VIL; -IO = 100A VCC = 2.0 V; VI = VIH or VIL; -IO = 100A VOH HIGH l level output ltt voltage out uts voltage; all outputs VCC = 2.7 V; VI = VIH or VIL; -IO = 100A VCC = 3.0 V; VI = VIH or VIL; -IO = 100A VCC = 4.5 V; VI = VIH or VIL; -IO = 100A VO OH HIGH level output g voltage; STANDARD outputs VCC = 3.0 V; VI = VIH or VIL; -IO = 6mA VCC = 4.5 V; VI = VIH or VIL; -IO = 12mA VCC = 1.2 V; VI = VIH or VIL; IO = 100A VCC = 2.0 V; VI = VIH or VIL; IO = 100A VOL LOW l ltt level output voltage out uts voltage; all outputs VCC = 2.7 V; VI = VIH or VIL; IO = 100A VCC = 3.0 V; VI = VIH or VIL; IO = 100A VCC = 4.5 V; VI = VIH or VIL; IO = 100A VO OL LOW level output voltage; g STANDARD outputs Input leakage current Quiescent supply current; MSI Additional quiescent supply current per input VCC = 3.0 V; VI = VIH or VIL; IO = 6mA VCC = 4.5 V; VI = VIH or VIL; IO = 12mA VCC = 5.5 V; VI = VCC or GND VCC = 5.5 V; VI = VCC or GND; IO = 0 VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V 1.8 2.5 2.8 4.3 2.40 3.60 1.2 2.0 2.7 3.0 4.5 2.82 4.20 0 0 0 0 0 0.25 0.35 0.2 0.2 0.2 0.2 0.40 0.55 1.0 20.0 500 0.2 0.2 0.2 0.2 0.50 V 0.65 1.0 160 850 A A A V 1.8 2.5 2.8 4.3 2.20 V 3.50 V 0.9 1.4 2.0 0.7II ICC ICC
NOTE: 1. All typical values are measured at Tamb = 25C.
1998 Apr 28
5
Philips Semiconductors
Product specification
Dual 2-to-4 line decoder/demultiplexer
74LV139
AC CHARACTERISTICS
GND = 0V; tr = tf 2.5ns; CL = 50pF; RL = 1K SYMBOL PARAMETER WAVEFORM CONDITION VCC(V) 1.2 2.0 tPHL/tPLH Propagation d l P ti delay nAn to Yn Figures 1, 2 2.7 3.0 to 3.6 4.5 to 5.5 1.2 2.0 tPHL/tPLH Propagation d l P ti delay nE to Yn Figures 1, 2 2.7 3.0 to 3.6 4.5 to 5.5 NOTES: 1. Unless otherwise stated, all typical values are measured at Tamb = 25C 2. Typical values are measured at VCC = 3.3 V. 60 20 15 112 27 20 16 13 34 25 20 16 ns MIN LIMITS -40 to +85 C TYP1 70 24 18 132 31 23 18 15 39 29 23 19 ns MAX -40 to +125 C MIN MAX UNIT
VM = 1.5 V at VCC 2.7 V and 3.6 V; VM = 0.5 V x VCC at VCC < 2.7 V and 4.5 V. VOL and VOH are the typical output voltage drop that occur with the output load.
Vl nAn INPUT GND tPHL VOH nYn OUTPUT VOL VM tPLH VM
AC WAVEFORMS
TEST CIRCUIT
Vcc
Vl PULSE GENERATOR RT D.U.T.
VO
50pF CL
RL= 1k
Test Circuit for Outputs DEFINITIONS
RL = Load resistor CL = Load capacitance includes jig and probe capacitiance
SV00535
RT = Termination resistance should be equal to ZOUT of pulse generators.
Figure 1. Address input (nAn) to output (nYn) propagation delays.
TEST tPLH/tPHL
VCC < 2.7V 2.7-3.6V 4.5 V
VI VCC 2.7V VCC
Vl nE INPUT GND tPHL VOH nYn OUTPUT VOL VM tPLH VM
SV00902
Figure 3. Load circuitry for switching times.
SV00536
Figure 2. Enable input (nE) to output (nYn) propagation delays.
1998 Apr 28
6
Philips Semiconductors
Product specification
Dual 2-to-4 line decoder/demultiplexer
74LV139
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
1998 Apr 28
7
Philips Semiconductors
Product specification
Dual 2-to-4 line decoder/demultiplexer
74LV139
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
1998 Apr 28
8
Philips Semiconductors
Product specification
Dual 2-to-4 line decoder/demultiplexer
74LV139
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
1998 Apr 28
9
Philips Semiconductors
Product specification
Dual 2-to-4 line decoder/demultiplexer
74LV139
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
1998 Apr 28
10
Philips Semiconductors
Product specification
Dual 2-to-4 line decoder/demultiplexer
74LV139
NOTES
1998 Apr 28
11
Philips Semiconductors
Product specification
Dual 2-to-4 line decoder/demultiplexer
74LV139
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-04424
Philips Semiconductors
1998 Apr 28 12

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